This invention relates to circuits that generate a reference voltage, and more particularly relates to bandgap voltage reference circuits.
The band-gap voltage reference circuit is widely used in various low-voltage applications, in order to provide a stable voltage reference. The band-gap voltage reference circuit operates on the principle of compensating the negative temperature coefficient of a base-emitter junction voltage, VBE, with the positive temperature coefficient of the thermal voltage VT, with VT being equal to kT/q, where where k is the Boltzmann constant, T is absolute temperature, and q is electron charge (1.6xe2x80xa210xe2x88x9219 coulomb). The variation of VBE with temperature, at room temperature, is xe2x88x922.2 mV/xc2x0 C., while VT is +0.086 mV/xc2x0 C. Note that since VT is Proportional To Absolute Temperature, it sometimes referred to using the acronym PTAT. Similarly, VBE is Complementary To Absolute Temperature, and so it is sometimes referred to using the acronym CTAT. The terms are combined to generate the band-gap voltage, VBG:
VBG=K1VBE+K2VT,xe2x80x83xe2x80x83Eq. (1)
where K1 and K2 are proportionality constants to ensure that the positive and negative thermal factors cancel one another, and, optionally, to scale the band-gap voltage to accommodate application requirements.
FIG. 1 is a circuit diagram showing a typical band-gap voltage reference circuit. The PMOS transistors M1, M2 and M3, bipolar transistors Q1 (having emitter area NA) and Q2 (having emitter area A), resistors R0, R1, R2 and R3 and operational amplifier (Op-amp) 101 are actual circuit elements. However, the voltage source 102 is merely representational, representing the offset voltage, VOS, of Op-amp 101. Transistors Q1 and Q2 conduct substantially equal currents. Because the ratio of the emitter areas of transistors Q1 and Q2 is N, a xcex94VBE, of substantially VTxe2x80xa2ln(N), is produced across resistor R0, providing a PTAT current. The Op-amp 101 forces the voltages at nodes V1 and V2 to be equal, thereby causing currents to flow in resistors R1 and R2 which are proportional to VBE, providing a CTAT current. The resulting current through transistors M1 and M2 is thus compensated in accordance with Equation (1). The compensated current is mirrored to transistor M3 to generate the output voltage VOUT.
Specifically, in the circuit of FIG. 1, the output voltage, VOUT, is:                                           V            OUT                    =                                                    R3                R1                            ·                              V                BE2                                      +                                          R3                R0                            ·                              V                T                            ·                              ln                ⁡                                  (                  N                  )                                                      -                                          (                                                      R3                    R1                                    +                                      R3                    R0                                                  )                            ·                              V                OS                                                    ,                            Eq        .                  xe2x80x83                ⁢                  (          2          )                    
where VBE2 is the base-emitter voltage of transistor Q2 and N is the area ratio of transistors Q1 and Q2 (i.e., NA/A). Comparing Equation (2) with Equation (1), it is clear that the values of resistors R0, R1 and R3, and the emitter areas of transistors Q1 and Q2 are selected to provide the desired proportionality constants K1 and K2.
However, a problem with the circuit of FIG. 1 is that the Op-amp 101 typically has substantial VOS, due, for example, to circuit asymmetries caused by device size mismatching. This offset causes an error to be introduced into the output voltage, VOUT, as can be seen in the last term in Equation (2). In addition, VOS is a temperature-dependent variable, due, for example, to VT mismatching of current mirrors and differential pairs within the Op-amp, so that this error varies with temperature. Note that Equation (2) shows that VOS is amplified by the factor       R3    R1    +      R3    R0  
in the generation of VOUT. In typical circuits, R3 is much larger R0, in order to achieve proper cancellation of the PTAT and CTAT factors, and therefore the error in VOUT caused by VOS is also large. In bandgap voltage reference circuits not using an Op-amp, but including a configuration like that of M1, M2 and M3 in FIG. 1, an offset between voltages at nodes V1 and V2 can also occur.
Solutions have been proposed to reduce the error in band-gap voltage reference circuit output caused by such voltage offset. One such proposed solution is to trim the resistors. However, such solution is expensive, and is neither area efficient or pin efficient, since additional silicon area must be devoted to the extra resistance that is trimmed, and at least one pin must be used to perform the trimming which, in some applications, must be dedicated.
Another proposed solution, in circuits using an Op-amp, is to design a low-offset Op-amp incorporating large devices and carefully chosen topology. However, this proposed solution is difficult in low-power and low-voltage applications.
A still further proposed solution is to cascade two bipolar transistors. However, like the low-offset Op-amp proposed solution, this is also difficult in low-voltage applications. Yet another proposed solution is to use a chopping amplifier for the Op-amp. However, this adds considerable complexity to the circuit.
It would therefore be desirable to have a band-gap voltage reference circuit that compensates for voltage offset, while overcoming the problems of prior art proposed solutions.
The present invention provides a bandgap reference circuit. The circuit includes a first current mirror having a first mirror transistor and a second mirror transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A first bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a predetermined size, is arranged to conduct a collector current from the first mirror transistor. A second bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a size that is proportional to the size of the emitter area of the first bipolar transistor, is arranged to conduct a collector current from the second mirror transistor, the base thereof being connected to the collector thereof. A first resistor is provided, in series with the collector of the second bipolar transistor and the second mirror transistor. The base of the first bipolar transistor is coupled to a common connection node of the first resistor and the second mirror transistor to substantially reduce the effects of offset error in the holding circuit. The holding circuit may be an operational amplifier.